ABOUT US


Steve Rideout
Principal Engineer
19 years of industry experience, including roles from individual contributor to technical project lead of 20 engineers
Responsible for development of 16 programmable device designs in the last 5 years
Including high performance and low cost FPGAs, and CPLDs
Xilinx and Altera devices
Experience with system and digital logic design for automatic test equipment / instrumentation, video cameras
Background of standard cell ASIC design including IBM and COT tool flows, with roles in architecture, RTL, synthesis, and physical design
Teradyne, Signal Communications
 
 
 
 
 
 
 
 
 
 
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